HPC Garage

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Vuduc Research Lab at Georgia Tech.

HotPar'10 paper accepted.

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Our paper describing our on-going work to study GPGPU acceleration for irregular scientific applications (sparse iterative solvers, sparse direct solvers, and the fast multipole method) has been accepted at HotPar'10.

  • R. Vuduc, A. Chandramowlishwaran, J. Choi, M. E. Guney, A. Shringarpure. "On the limits of GPU acceleration." In Proc. USENIX Workshop on Hot Topics in Parallelism (HotPar), Berkeley, CA, USA, June 2010. (to appear)
 

Best paper at IPDPS'10!

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IPDPS'10 Logo

We just got word that Aparna's, Kath Knobe's (Intel), and my paper will get the Best Paper Award in the software track at the IEEE Int'l. Parallel and Distributed Processing Symposium (IPDPS), which will be held here in Atlanta in April. The paper is the first performance evaluation of a relatively new parallel programming model, called Concurrent Collections (CnC), on state-of-the-art multicore systems. It shows of CnC's extraordinary potential, using examples from dense linear algebra.

Congratulations to the team. We owe many thanks to our friends and colleagues at Intel (Frank Schlimbach, Geoff Lowney, Shin Lee, and CK Luk) and Rice University (Vivek Sarkar and Zoran Budimlić) for their feedback, encouragement, and support during the course of this work. 

 

 

Paper accepted at ICSE '10!

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Sangmin Park's paper on fault localization applied to concurrent programs has been accepted for publication! The paper will appear at the ACM/IEEE International Conference on Software Engineering (ICSE), to be held in Cape Town, South Africa in May 2010. This paper describes a novel technique for pinpointing the cause of program failure in multithreaded Java software. Sangmin designed and implemented this approach in a prototype tool called "Falcon." This effort is joint between Prof. Mary Jean Harrold (Sangmin's primary advisor) and The HPC Garage.

 

Two papers @ IPDPS'10.

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The HPC Garage will have two papers at the upcoming IPDPS conference, to be held here in Atlanta, April 19--23. Congratulations to Aparna, who led the two papers, as well as our colleagues at Intel (Kath Knobe) and Lawrence Berkeley National Laboratory (Sam Williams and Lenny Oliker) for their significant contributions!

Here's a brief description of the papers ...

Read more...
 

Vuduc at the R&D 100 Awards.

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Rich just returned from the R&D 100 Awards Ceremony, where colleagues from Lawrence Livermore National Laboratory (LLNL), Vienna University of TechnologyUniversity of Texas at San Antonio, and Indiana University, and he received an award for the ROSE Compiler InfrastructureDr. Dan Quinlan at LLNL leads the effort. Congratulations to the team!

Rich + R&D 100 Awards Plaque 

 

Autotuning @ Tahoe.

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CScADS 2009 Autotuning Workshop Attendees The US DOE-sponsored workshop on Libraries and Autotuning for Petascale Systems, held from Aug. 10–12 in Tahoe City, California, just completed. Jack Dongarra, Keith Cooper, Kathy Yelick, and Rich co-organize this annual research meeting. Perhaps not surprisingly, the most contentious discussion took place on the definition of autotuning!

The meeting slides are posted here: http://www.cs.utk.edu/~dongarra/cscads-libtune09.htm

 

 

Multicore SpMV paper is top ParCo download (Q1 '09).

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Our co-authored paper on multicore optimizations for sparse matrix-vector multiply was the “hottest” (most downloaded) Journal of Parallel Computing (ParCo) article in Q1 2009. 

[ParCo Top 25 List, Q1 2009] S. Williams, L. Oliker, R. Vuduc, J. Shalf, K. Yelick, J. Demmel. “Optimization of sparse matrix-vector multiplication on emerging multicore platforms.” J. Par. Comput. (ParCo), 35(3), pp. 178—194, March 2009. doi:10.1016/j.parco.2008.12.006

 

At PPoPP 2010.

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The HPC Garage is in Bangalore, India this week for the ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP). Jee and Amik present our paper on model-driven autotuning for GPUs today; and Aparna also presents a poster on our Concurrent Collections applications work.

HPC Garage at PPoPP 2010 in Bangalore, India.

 

Bon voyage to Csaba.

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Today was the last day for Csaba Vigh, a visiting student from Technische Universität München under Prof. Michael Bader. Csaba worked with Prof. George Biros and Rich on performance analysis and tuning of Csaba's adaptive grid codes, which use cache-efficient space-filling curve traversals. Though Csaba he'll be missed, we look forward to a long continued collaboration!

Csaba and Rich in the HPC Garage

 

GT/HPC @ SC'09!

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Be sure to stop by the Georgia Tech booth at SC'09. To read about our activities and presence at this premier venue for HPC research, click here or visit the HPC@GT website. Come see the talk for our paper on Tuesday, Nov. 17th at 3:30pm PST in Portland Ballroom 255---this paper was nominated for the conference's Best Technical Paper award. This work is joint with the Prof. Biros' CSELA lab.

GT Booth @ SC'09 

PhotoVirat Agarwal (IBM+GT PhD), Aparna (HPC Garage PhD student), and Kamesh Madduri (GT alum, now @ LBNL) posing as “booth babes” at the GT booth at SC'09.

 

PPoPP'10 paper on GPU SpMV.

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Jee's and Amik's paper on autotuning sparse matrix-vector multiply for GPUs will appear at PPoPP 2010 in Bangalore, India. Great work, gang!
 

ROSE wins an R&D 100 award!

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Congratulations to the ROSE Compiler Project (LLNL), which just won an R&D 100 Award for 2009. Rich is a contributing collaborator to ROSE. See http://www.rosecompiler.org.

R&D Magazine Logo
 

Best paper nominee at SC'09!

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Congratulations to Aparna and Aashay for their contributions to a paper that has been accepted to Supercomputing and, moreover, is a best paper nominee! This paper, led by Ilya Lashuk and Prof. George Biros, discusses a highly scalable implementation of the kernel-independent fast multiple method, with experimental runs up to 65k cores and 256 GPUs.

Read more...
 


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