This page contains slides for Rich Vuduc's talk at MEMSYS'16, October 4, 2016.

Your public critiques (and praise) are welcome: @hpcgarage

• [iCloud (password required) | PDF slides (~ 38 MiB)] “How much (execution) time, energy, and power does my algorithm need?”

This work is generously supported in part by a grant from the National Science Foundation (Award 1422935), among other earlier grants.

Links to some of the key papers referenced in this talk:

• J. Choi, D. Bedard, R. Fowler, R. Vuduc. “A roofline model of energy.” In IPDPS'13.
• K. Czechowski, R. Vuduc. “A theoretical framework for algorithm-architecture co-design.” In IPDPS'13.
• J. Choi, X. Liu, M. Dukhan, R. Vuduc. “Algorithmic time, energy, and power on candidate HPC building blocks.” In IPDPS'14.
• K. Czechowski et al. “Improving the energy efficiency of big cores. In ISCA'14.
• O. Green, M. Dukhan, R. Vuduc. “Branch-avoiding graph algorithms.” In SPAA'15.
• A. Davidson, S. Baxter, M. Garland, J. Owens. “Work-efficient parallel GPU methods for single-source shortest paths.” In IPDPS'14.
• J. Choi, R. Vuduc. “Analyzing the energy-efficiency of the fast multipole method using a DVFS-aware energy model.” Heterogeneous Computing Workshop, 2016.