Piyush is back from the 8th International Workshop on Parallel Matrix Algorithms and Applications (PMAA 2014), where he spoke about his work on the concept of a self-stabilizing iterative solver, which could still compute a correct answer in the presence of temporary random numerical bit-flips. Click [here] for a copy of his slides.

Piyush's selfie from PMAA 2014

Piyush’s selfie from PMAA 2014


Rich is spending the week at ETH Zürich attending the Platform for Advanced Scientific Computing (PASC) Conference. Many thanks to two of the co-organizers, Markus Püschel and Olaf Shank, for being great hosts!

If you are interested in getting a copy of Rich’s talk slides + related material, see:

View form Villa Hatt

The view from Villa Hatt at ETH Zürich is not too shabby!


Jee and Rich are in Phoenix this week for IPDPS’14, where Jee will present his latest updates to his “energy roofline” model [Tue May 20, Session 11] :

Rich also has the pleasure of serving in a panel discussion at the High-Performance, Power-Aware Computing workshop. His position is that power-aware scheduling is really an optimal control problem. For his 1-slide summary, see: [link]

Outside our group, Georgia Tech has a very strong representation this year. Looking at the program, we count 9 papers, including two of the four “Best Papers.” Go, Buzz!

Jee chowing down on a pre-conference pulpo at Mariscos Sinaloa.

Jee chowing down on a pre-conference pulpo at Mariscos Sinaloa.

ISCA’14 paper to appear

Kent, in collaboration with Victor Lee among others at Intel, has an exciting new paper that will appear at ISCA’14. It teases apart the improvements in energy-efficiency due to process technology improvements and microarchitectural changes. Congrats to Kent, Victor, and the rest of the Intel team. We’ll post a preprint when it’s ready; stay tuned!


Jee is back from GPGPU-7, where he is presenting some new work on a hybrid CPU+GPU implementation of the kernel-independent fast multipole method, or FMM.

  • Jee Choi, Aparna Chandramowlishwaran, Kamesh Madduri, Richard Vuduc. “A CPU-GPU hybrid implementation and model-driven scheduling of the fast multipole method.” In Proc. 7th Wkshp. General-Purpose Processing using GPUs (GPGPU-7), Salt Lake City, UT, March 2014. [Paper|Slides]
Jee & Naila @ GPGPU-7

Representing Georgia Tech at GPGPU-7, Jee and Naila (from a different research lab)


Piyush, Jee, and Rich are in Portland representing the lab at the SIAM Parallel Processing ’14 meeting. If you are also there, please drop by our various events! List below; resources (papers, slides) are here: [link].

Check us out at SC’13!

We have a number of activities happening at SC’13 — if you are there at the Denver Convention Center this year, please check us out!

In addition, Georgia Tech has its usual large presence at SC13. See for details.


(L-to-R) Piyush, Marat, and Jee at SC'13

(L-to-R) Piyush, Marat, and Jee at our lab pre-conference celebratory dinner. Have a great meeting, gang!


Rich just returned from the Workshop on Visualization and Analysis of Performance of Large-scale Software (VAPLS), co-located with IEEE Vis. The workshop featured a number of very compelling use of visualization to aid performance analysis, which in the long run will help make performance engineering more productive, accessible, and best of all, fun!

Rich’s talk materials appear here: [www]

An example of abstractly visualizing communication volume on an AMR tree.

An example of abstractly visualizing communication volume on an AMR tree, taken from one of the other presenters (see VAPLS’13 website).

Dagstuhl 13401

This week Rich has the great fortune of attending Dagstuhl Seminar 13401: Automatic Application Autotuning for HPC Architectures. He’ll be summarizing Jee’s work (with critical assists by Marat) on the energy archline model. For his slides and pointers to relevant materials, look here: [www]

"Classical" wing of Schloss Dagstuhl

“Classical” wing of Schloss Dagstuhl

Yeppp! 1.0 is live

Marat recently released version 1.0 of his Yeppp! library, which includes fast portable implementations of vector elementary functions (e.g., log/exp, trigonometric functions) and polynomial evaluation. See: